Signal acquisition can be an important step for discrete time signal processing. The integrity of the signal acquired often limits the overall circuit performance of discrete time signal conditioning circuits, analog-to-digital converters, switch cap filters, etc. FIG. 1A is a circuit diagram of a basic switched capacitor (or switched cap) sampling circuit 105, in which the switch is a transmission gate (T-gate) that accommodates input signals from rail to rail. The T-gate includes an n-type metal oxide semiconductor (NMOS) transistor 102 and a p-type metal oxide semiconductor (PMOS) transistor 104. The capacitor represents the load to the T-gate and the signal Q is the sampling clock signal. FIG. 1B is an illustration of the ON impedance RON of the T-gate in FIG. 1A. Ideally RON is small and the variation with input voltage VIN is as flat as possible so that the sampled signal has minimal distortion. In practice, the T-gate RON is much higher when the input signal VIN is right at midrange between a low VIN and a high VIN, where both the PMOS and NMOS transistors are barely turned on due to the relatively large threshold voltage VTH. This is especially true when the supply voltage is low as in advanced complementary metal oxide semiconductor (CMOS) technologies. Thus there is a need for improved performance of sampling circuits.